Conventional CMOS (Complementary Metal-Oxide-Semiconductor) SRAM cells consist of planar MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) on silicon substrates such as bulk wafer or SOI (Silicon On Insulator) wafer. Reduction in the device dimension has been performed for the purpose of enhancing performance such as integration density and operation speed, however, recently, it conversely increases the short channel effect and threshold voltage variations. As a result, leak current during a memory holding operation tends to occupy a large portion of the total power consumption in the SRAM device using planar MOSFETs.
For the purpose of suppressing the leak current and realizing low power consumption, Patent Document 1 mentioned below and others disclose a technology to reduce a standby current by varying the supply voltage supplied to a memory cell in response to the operation of the cell and utilizing effectively the substrate bias effect caused thereby.
In the device described in Patent Document 1, when the cell is accessed, the supply voltage of the cell is controlled so as to apply the entire voltage between the higher voltage source and the ground levels to the cell. When the cell is not accessed, the potential at a node on the low potential side of the cell is set higher than the ground potential. Thus, the leak current is reduced due to the substrate bias effect and the reduced supply voltage.
However, reduction in the supply voltage amplitude induces reduction in noise margin. This reduction in noise margin becomes a severe problem since the more the feature size of the transistor is reduced, the more the threshold voltage variations increase (See Non-Patent Document 1 mentioned below).
One of the alternative ways to realize low power consumption by reducing the supply voltage amplitude is to vary the substrate bias voltage row by row. In other words, in order to prevent the leak current, unaccessed cells are operated at a higher threshold voltage by applying a lower the substrate bias voltage than that of accessed cells.
However, in the SRAM device using conventional bulk planar MOSFETs, it is not possible to apply different substrate bias voltages row by row. This is the reason why the supply voltage has been varied. For applying different substrate bias voltages row by row in the bulk planar MOSFET, it is required to introduce a process to electrically separate each well, which further requires additional areas on a chip.
In addition, according to Non-Patent Document 1, it will be more difficult for the bulk planar MOSFET to suppress increase of the short channel effect. This means that the leak current will also increase. Accordingly, it is likely that the increases in the chip area and process cost do not have much effect.    [Patent Document 1] Japanese Unexamined Patent Application Publication 2004-206745.    [Non-Patent Document 1] ITRS 2005, International Technology Roadmap for Semiconductor 2005 edition, http://public.itrs.net